The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device using a self-aligned contact and a method for manufacturing the same.
Generally speaking, to increase the integration of a semiconductor memory device, research into fields such as lithography, cell structure, new wiring materials, and the physical properties of insulating films becomes essential. Specifically, when increasing the integration of a DRAM device from 4 Mbit to 256 Mbit, it becomes necessary to reduce the size of a contact area of the device along with the cell area reduction.
Though a contact is formed to a minimum feature size, the inadvertent exposure of a peripheral structure, (e.g., a gate electrode or a bitline), frequently occurs due to mask misalignment. Thus, an electrical short may result between the gate electrode and the bitline, between the bitline and a storage node, or between the gate electrode and the storage node, which is a severely detrimental to the reliability of the memory device.
Many methods have been developed for avoiding such an exposure of the peripheral structure due to mask misalignment. One among these is a method for forming a self-aligned contact.
The method for forming a self-aligned contact is one in which the contact is formed using the step differential of a peripheral structure. Since contacts of various sizes are obtained without using a mask according to peripheral structure height, insulating material thickness at the point where the contact hole will be formed, and the etching method, this method is suitable for realizing a highly integrated semiconductor device.
A method for manufacturing a semiconductor device using a self-aligned contact, which is disclosed in German Patent Publication No. 3,910,033 A1, will be explained with reference to FIGS. 1, 2 and 3.
Referring to FIG. 1, a gate oxide film (not shown) is formed on a semiconductor substrate 1 having a field oxide film 2 formed thereon, and a polycrystalline silicon and an insulating material are sequentially deposited on the gate oxide film. Then, the insulating material layer and the polycrystalline silicon layer are patterned by a lithography process, thereby forming a gate electrode 3 which is capped by an insulating layer 4. Thereafter, an oxide is deposited on the resultant structure wherein gate electrode 3 is formed. The oxide is anisotropically etched to thereby form a spacer 5 on the sidewalls of gate electrode 3 and insulating layer 4. Then, impurity ions are implanted throughout the entire surface of the resultant structure having spacer 5, thereby forming an active region 20 in substrate 1 serving as a source/drain region. Here, the gate oxide film on the surface of substrate 1 is also etched during the anisotropic etching process for forming spacer 5, to thereby form a contact hole (not shown) which is self-aligned by spacer 5. Then, an impurity-doped polycrystalline silicon is deposited on the resultant structure wherein the self-aligned contact is formed, and is patterned by a lithography process, thereby forming a pad electrode 22 which is connected with active region 20 through the self-aligned contact.
Referring to FIG. 2, an insulating material, e.g., boro-phospho-silicate glass (BPSG), is deposited on the resultant structure wherein pad electrode 22 is formed and is reflowed at a high temperature, thereby forming a first planarizing layer 24. Then, first planarizing layer 24 is selectively etched by a lithography process, thereby forming a bitline contact 26 to expose a pad electrode 22. Thereafter, a conductive material is deposited on the resultant structure wherein bitline contact 26 is formed and is patterned by a lithography process, thereby forming a bitline 28 which is connected with pad electrode 22 through bitline contact 26. Here, pad electrode 22 guards against the creation of a short between gate electrode 3 and bitline 28 during the formation of bitline contact 26.
Referring to FIG. 3, an insulating material, e.g., BPSG, is deposited on the resultant structure wherein bitline 28 is formed, and is reflowed to thereby form a second planarizing layer (not shown). Then, the second and first planarizing layers are selectively etched by a lithography process, thereby forming a storage-node contact 30 to expose pad electrode 22. Thereafter, an impurity-doped polycrystalline silicon is deposited on the resultant structure wherein storage-node contact 30 is formed, and is patterned by a lithography process, thereby forming a capacitor storage node 32 which is connected with pad electrode 20 through storage-node contact 30. Here, pad electrode 22 guards against the creation of a short between gate electrode 3 and storage node 32 during the formation of storage-node contact 30.
According to the above-described conventional method, since the insulating layer and the spacer enveloping the gate electrode, and the field oxide film are used as an etch-blocking layer during the formation of the pad electrode, the substrate of the active region may be damaged when the size of the field oxide film is small or when the pad electrode is misaligned. In DRAMs beyond the 64 Mbit capacity, the opposing bird's beaks of the field oxide film meet each other during the oxidation step for field oxide film formation, so that punch-through occurs. Thus, it is very difficult to reduce the size of the active region and increase the size of the field oxide film as desired. Therefore, it is hard to effectively prevent damage to the active region when forming the pad electrode. Also, since the bitline can be aligned to the bitline contact only when the bitline contact is precisely aligned between the gate electrode and the active region, the alignment tolerance of the bitline contact is independent of the size of the pad electrode. Accordingly, the pad electrode cannot help in obtaining a sufficient misalignment margin of the bitline contact. Also, since the storage-node contact is aligned between the bitline and the gate electrode, for preventing a short between the storage node and the bitline, the storage-node contact should be formed with respect to an alignment margin (reference symbol "M" in FIG. 3) with respect to the bitline. Therefore, the pad electrode also cannot contribute to the securing of a sufficient misalignment margin of the storage-node contact.